1. Field of the Invention
The present invention relates to an image information transmission system for transmitting image information.
2. Related Background Art
A MIN-MAX method is available as a conventional method of encoding a television signal and reducing the average number of bits per sample in order to obtain a narrow transmission band of the encoded television signal.
The MIN-MAX method will be described below.
A television signal has high two- or three-dimensional correlation. When pixels of an image representing the television signal are divided into small blocks, a pixel level of each block often has only a narrow dynamic range due to local correlation. When a dynamic range of the pixel level in each block is obtained and adaptive coding is performed, the television signal can be compressed with high efficiency.
The MIN-MAX method will be described in more detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing a schematic arrangement of a data transmission side in a conventional image information transmission system. A raster-scanned analog image signal such as a television signal is sampled at a predetermined frequency, and n-bit digital image data is input to a terminal 101. This 2.sup.n gray-level digital image data is supplied to a pixel block division circuit 102. FIG. 2 is a view showing a state wherein all pixel data of one frame are divided into pixel blocks. In the pixel block division circuit 102, as shown in FIG. 2, all pixel data of one frame are divided into a plurality of pixel blocks such that the number of pixels of each pixel block in the horizontal direction (to be referred to as an H direction hereinafter) is l, and the number of pixels of each pixel block in a vertical direction (to be referred to as a V direction hereinafter) is m. That is, each pixel block consists of (l.times.m) pixels. The pixel block division circuit 102 outputs pixel data in units of pixel blocks.
FIG. 3 is a view showing a structure of each pixel block. The pixel block consists of D.sub.1.1 to D.sub.m.l pixel data. The pixel data output in units of pixel blocks from the pixel block division circuit 102 is input to a maximum value detection circuit 103, a minimum value detection circuit 104, and a timing adjusting circuit 105. Of all the pixel data D.sub.1.1 to D.sub.m.l, pixel data representing a maximum value (D.sub.max) and a minimum value (D.sub.min) are detected by and output from the detection circuits 103 and 104, respectively.
The timing adjusting circuit 105 delays all the pixel data by a time period required for causing the maximum and minimum value detection circuits 103 and 104 to detect the maximum and minimum values D.sub.max and D.sub.min. The pixel data are supplied to a division value conversion circuit 106 in a predetermined order in units of pixel blocks, e.g., in an order of D.sub.1.1, D.sub.2.1, D.sub.3.1, . . . D.sub.m.1, D.sub.1.2, . . . D.sub.m.2, . . . D.sub.1.(l-1), . . . D.sub.m.(l-1), D.sub.1.l, . . . D.sub.m.l.
All the pixel data D.sub.1.1 to D.sub.m.l and the maximum and minimum values D.sub.max and D.sub.min of each pixel block are input to the division value conversion circuit 106. A difference between the maximum and the minimum values D.sub.max and D.sub.min of each pixel data is divided into 2.sup.k (where k is an integer smaller than n) regions, and quantization levels of these regions are represented by k-bit division codes .DELTA..sub.1.1 to .DELTA..sub.m.l to detect a correspondence between each pixel data and a corresponding region. In place of each pixel data, a division code representing the corresponding region to which the pixel data corresponds is output. The quantization state is shown in FIG. 4(a).
shown in FIG. 4(a), .DELTA..sub.i.j is output as a k-bit binary code. The resultant k-bit division code .DELTA..sub.i.j and n-bit maximum and minimum values D.sub.max and D.sub.min are converted into serial data by parallel-to-serial (P-S) converters 107a, 107b, and 107c, respectively. The serial data is converted into serial data (FIG. 5) by a data selector 108. FIG. 5 shows transmission data for one pixel block.
The time base of data output from the data selector 108 is controlled by a first-in first-out (FIFO) memory 109 so as to obtain a constant data transfer rate. A synchronizing signal is added to an output from the FIFO memory 109 by a synchronizing signal addition circuit 110. The resultant signal is output from an output terminal 111 onto a transmission line (e.g., a magnetic recording/reproducing system such as a VTR). The synchronizing signal can be added to the output from the FIFO memory 109 for every pixel block or every plurality of pixel blocks. Timing of the respective circuit components are determined on the basis of timing signals output from a timing controller 112.
FIG. 6 is a block diagram showing a schematic arrangement of a data reception side corresponding to the data transmission side shown in FIG. 1. Referring to FIG. 6, transmission data encoded by the MIN-MAX method at the transmission side is input to a terminal 121. The synchronizing signal included in the input transmission data is separated by a synchronizing signal separation circuit 122 and is supplied to a timing controller 123. The timing controller 123 generates various timing signals for controlling operation timings of the respective circuit components on the reception side on the basis of the synchronizing signal supplied to the timing controller 123.
A data selector 124 divides the input transmission data into n-bit maximum and minimum value data D.sub.max and D.sub.min and the k-bit quantized codes .DELTA..sub.i.j obtained by k-bit quantizing the pixel data between the maximum and minimum values D.sub.max and D.sub.min. The data D.sub.max and D.sub.min and the code .DELTA..sub.i.j are converted into parallel data by serial-to-parallel (S-P) converters 125a and 125b, respectively. The maximum and minimum value data D.sub.max and D.sub.min of each pixel as parallel data from the S-P converter 125a are latched by latch circuits 126 and 127, respectively. The codes .DELTA..sub.i.j are converted into all pixel data D.sub.1.1 to D.sub.m.l within each block by a division value inversion circuit 128 on the basis of the data D.sub.max and D.sub.min latched by the latch circuits 126 and 127. The pixel data are then input to a scan converter 129. The scan converter 129 outputs image data from a terminal 130 in response to a timing signal generated by the timing controller 123.
In the conventional image transmission system, quantization of a difference between a pair of data associated with the maximum and minimum values is predetermined regardless of the characteristics of an image in each block. That is, a technique for quantizing a pixel block including a portion (edge portion) in which image data between the adjacent pixels greatly change is equal to a technique for quantizing a pixel block representing a portion (flat portion) in which image data between the adjacent pixels do not greatly change. Therefore, the quantization techniques may not be suitable for the characteristics of the image data, and pixel blocks for which the quantization techniques are not suitable are typically subjected to an increase in quantization noise.